The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.
Thus, packages such as wafer level packaging (WLP) have begun to be developed, in which integrated circuits (ICs) are placed on a carrier having wiring for making connection to the ICs and other electrical components. In an attempt to further increase circuit density, three-dimensional (3D) ICs have also been developed, in which two dies or ICs are bonded together electrical connections are formed between the dies and contact pads on a substrate. These relatively new types of packaging for semiconductors face manufacturing challenges such as poor adhesion between the die and carriers, warpage, die shifting, poor moisture and photo pollution, and other reliability issues.